core-v-verif
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openhwgroup
Update CSR-access test
cv32e40s_csr_template.yaml was updated in #1328, this issue serves as a remainder to generate a new test-section for the csr_access_test. (Test is automatically generated with some minor hand-modified sections)
csr_access_test script (from riscv-dv) does not support our interpretation of WARL - all bits in WARL-defined register fields are assumed fully RW by the test generator.
One example: write: 0x5a5a_5a5a to mstatus, reads back: 0x0020_0080, while test generator expects 0x0020_1880 to be read back due to the WARL definition.
Yes, WARL is a software concept that makes sense for ABI users, but not for RTL developers and verifiers. I had though that declaring fields RW (not WARL) would resolve this issue. If this is not the case, we should consider modifying/extending the test generator to fix the problem.
Hi @silabs-hfegran, how was this issue resolved? Was a modification of the CSR test-generator required? If so, can you point to the associated PR? Thanks.
https://github.com/silabs-hfegran/riscv-dv/commit/0b707d80452d2f7dcf68012645fc4ae6bbae2f1c (This is also present on upstream riscv-dv), there is a "legalize-warl"-functionality added to the script, that enables one to define the warl-behavior of a register with python in the yaml definition file.