core-v-verif

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add instance macros for DSIM for all functional coverage groups

1

### Type Indicate whether the type of problem you found: * Functionally incorrect behavior ### Steps to Reproduce The DSIM simulator should not use options.per_instance = 1 for all functional...

strichmo

### Task Outcome A reviewed ISA vplan for the Zce is created. The Vplan should cover the Zcea, Zceb, and Zcee sub-extensions of Zce. ### Background information The vplan should...

strichmo

### Task Outcome The master implementation of the driver and sequence items in the uvma_obi_memory agent need to be implemented to fully satisfy 1p2 standards. ### Background information The current...

strichmo

CV32E41P "hello-world" program checks for E40P value of marchid

1

This is a bug in both the RTL and TB. The current value of the CV32E41P `marchid` CSR is 0x4. This is inherited from the CV32E40P and must be changed...

MikeOpenHWGroup

core-v-verif is using quite outdated RISC-V compliance tests. By now (i.e. end of last year) ‘framework 2’ has been introduced and ‘framework 3’ is being worked on, see https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/Luf6uWuAAlU. Issue...

Silabs-ArjanB

OBI UVM Agent may need to support atomic transactions

1

### Task Outcome The OBI UVM agent properly supports atomic transactions ### Background information In the current active slave implementation of the OBI UVM Agent, ### Location Information lib/uvma_agents/uvm_obi_memory ###...

strichmo

In [cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv ](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv#L118) the size of an array is based on a hard-coded "magic number". This should be based on a parameter or macro. I recommend using [this](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv#L23) one. ###...

MikeOpenHWGroup

Investigate build_phase implementation of `uvma_core_cntrl_agent_c`

2

The [uvma_core_cntrl_agent_c](https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_agent.sv) agent is a component of the [core-v-verif library](https://github.com/openhwgroup/core-v-verif/blob/master/lib) of reusable UVM Agents. The cv32e40x extends this agent to create [uvma_cv32e40x_core_cntrl_agent_c](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_agent.sv). DSIM runs of the cv32e40x environment experience a...

MikeOpenHWGroup

### Task Outcome The OBI memory model (i.e. the new UVM agent) should be able to randomly assert gnt to exercise OBI protocol in that gnt can be randomly asserted...

strichmo

This task is related to issue #721. The core testbench is peppered `ifdef VERILATOR` (or `ifndef VERILATOR`) macro checks to exclude compilation of UVM, assertions, etc. @pascalgouedo came up with...

MikeOpenHWGroup