alexforencich
Add license need to ZCU102 reference design
ZCU102 SoC part requires a Vivado license. This is the result from experimentation as reported at https://github.com/alexforencich/verilog-ethernet/issues/146#issuecomment-1429328609.
To improve usability, this simply addition hints users to consider setting up the license before make-ing the code and/or use the eval one.
TBH, I think most of the target boards need a license of some sort. So it might make sense to add a "licenses required" section or something to all of the readmes, not just the ZCU102. I think for this repo, either no license is required, or a toolchain license is required. For Corundum, in addition to toolchain licenses, 100G designs for Xilinx parts need separate (but no-charge) CMAC licenses, but this should be noted in the main readme and in the docs. Perhaps instead of updating all of the readmes, it might make sense to add a readme to the example folder detailing this sort of stuff.
Yeap, it makes sense what you're suggesting above. Just tested with a few other supported boards I've got around and encountered the same situation.
Happy to take action on it myself or defer to you if that's faster/preferred. Let me know how you'd like to move forward.
If you want to do something that's fine, I just don't want to arbitrarily single out one board.
Updated the README of those reference design examples using Vivado (left aside the ones using ISE, as I'm unsure whether license's needed there). Back to you @alexforencich.
Well, tbh I think it makes sense only to include this sort of disclaimer for targets that aren't covered by Vivado standard edition or ISE web pack, such as the Nexys Video, all Alveo boards, the X10 and X25, Atlys, and Arty.
And also specifying "to build the IP core" is a bit odd because in most cases the license is for Vivado bitstream generation, not for a specific core. Well, with the exception of the NetFPGA SUME, which I think requires a no-charge PCS/PMA license in its current incarnation.