alexforencich
VCU 128 Support!
I am trying to set up an ethernet connection with Xilinks VCU 128, however the board is not responding. So, does the code in this repo for 118 VCU is off-the-shelf applicable to VCU 128? Or I need to edit the code and if you could give some tips on the nuances in the modified code?
Don't know, I don't have access to a VCU128. Some modifications are likely required; check the schematic vs. the constraints file and top-level ports.
Hi @alexforencich we have updated the constraint file from VCU118 to VCU128. There is no pin for PHY1_RESET_B in the FPGA so we connected it to PHY1_PDWN_B_I_INT_B_O.
We also had to change the nibble settings as follows (based on your note in the xilinx forum here and based on the comments here)
RxNibbleBitslice0Used: false InstantiateBitslice0: true TX_in_upper_nibble: true TX Lane 0: DIFF PAIR 1 RX Lane 0: DIFF PAIR 2
It also created a dummy NC port which we LOC properly.
Since both VCU118 and VCU128 uses the same DP83867ISRGZ, I assume mdc mdio settings don't need to be changed. However, the board didn't ping. Do you have any suggestions what else may need to be changed? Thanks a lot for your time.
Look at the SGMII core status vector, try forcing the link to other speeds, connect the ILA and look at the GMII signals.
Alternatively, if you donate a VCU128, I'll sort all of this out and add an example design for it.