cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
This PR is part of the parametrization task
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, I got a SoC project using CVA6 cores,...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When XLEN=32bits, RVD cannot be enabled. This is an...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description During the HPDCache, some limitations have detected in AXI...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In the CVA6 implementation, when the fdiv.s instruction is...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Verification script `verif/sim/cva6.py` performs version consistency checks on several...
The following error occurs when I run this step.     When I look up the tools path, I find that spike doesn't exist.  So I tried...
On a local clone of the repository, I ran the `dv-riscv-arch-test.sh` script and experienced a test failure for the `riscv-test-suite/rv64i_m/B/src/zext.h_64-01.S` test in verilator. I first assumed something was set up...
To fix #2012 The previous code would fail to exit normally under certain circumstances. For example, before exiting, `a0=0b01` (which becomes `0b10` after left shifting), so it is necessary to...
## WHAT - gsoc 2024 project: [Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache](https://fossi-foundation.org/gsoc/gsoc24-ideas#transforming-the-openhw-high-performance-data-cache-into-a-high-performance-instruction-cache) - extend hpdcache (high performance data cache) so that it can...