cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
**Background** **What (objective description)** **How To** **Current Status** **Risks** **Prerequisites** **KPI** **Description of DONE**
***What (objective description) ?*** Create ISA DV plan for embedded config ISA. ***How to ?*** Use the ISA DV plan of the Step1 configuration , and add to it the...
Hi, I was working on CVA6 CSR access mode verification and I found that as per CVA6 user manual reset value for MTVEC CSR is zero, but in CVA6 RTL...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I create a new issue, similar to #1071, but...
Add in Github's CI a 64-bit configuration of the CVA6 using the HPDcache and restore WB cache test
This PR adds to the Github's CI a tests with the cv64a6_imafdc_sv39_hpdcache configuration. This configuration uses 64-bit variant of the CVA6 with "deep" structures related to the data cache: -...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi @Saute0212 @JeanRochCoulon I guess an issue is more...
Update of user manual related to MMU Unification
Update of design document related to MMU Unification
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Red Semi is trying to get Linux running on...