cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Hi, I am doing the verification of cva6. I want to know how start address is generating or assigned as per the linkers script inside verif/tests/. May I know how...
Hi, I observed that in the **cva6_tb_wrapper.sv file**, 1. we are connecting axi_interface signal based on axi_switch_vif as done in below assign statement ****assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready :...
Hi, We want to integrate the uart in cva6. We have integrated uart in cva6 the way it is shown in the ariane _peripherals.sv file. But we are not seeing...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When switching WT cache to HPD cache, 4 AXI...
In order to aligned the ways address translation is managed between FETCH and DATA the address translation request is moved from the icache to the frontend. The change is supposed...
### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description In current version of CVA6, for interrupts, vector mode...
Disable some bits when RVU or RVS not present
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, As agreed, we (CEA) hae reviewed the AXI...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Utilizing an updated AXI agent (PR #2416), a generated...
PR for the incoming changes to core-v-verif (not already merged)