cva6

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### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Refer to #1498

JeanRochCoulon

[TASK] Cascade CPU fuzzing research bugs track

7

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Recently the paper: _Cascade: CPU Fuzzing via Intricate Program...

acaldaya

[TASK] CSR spec for embedded configuration

2

### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Add CSR spec for embedded configuration ### Required Changes...

ASintzoff

[TASK] MMU Architectural DV Plan Execution

2

### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Add a comprehensive set of self-checking assembly tests to...

fatimasaleem

[TASK] Condition RTL with RVFI parameter

3

### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Condition RTL with RVFI parameter to remove the related...

JeanRochCoulon

[TASK] Use cva6.py to simulate cva6 and clean-up env setup

3

### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Support only cva6.py commands to simulate cva6. Today two...

JeanRochCoulon

CVA6 Makefile sets random seed to "1"

1

The Makefile at `core-v-verif/cva6/sim/Makefile` "hardwires" the random seed: ``` ALL_SIMV_UVM_FLAGS = -licwait 20 -l +ntb_random_seed=1 \ ``` I see that `core-v-verif/cva6/sim/cva6-simulator.yaml` _appears_ to offer the ability to override this: ```...

MikeOpenHWGroup

CVA6 CSR spike discrepancies list

9

HI, Please find the below list of CSRs which has discrepancies between CVA6 and spike     Sl no | Name | Address Offset | Width | Access Type |...

spidugu444

[TASK] Add CSRs and MEM read info to CVA6 RVFI

2

**Background** CSR state information (either full state or change sets) is necessary to verify the RTL behavior against the Reference Model (the Spike ISS). In mainline Spike the CSR state...

zchamski

[TASK] investigate possible FPGA build time optimizations

2

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description https://github.com/openhwgroup/cva6/pull/1535 reduced the number of jobs run for each...

cathales