feat: extended hpdc cache subsystem

[takeshiho0531]

WHAT

• gsoc 2024 project: Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache
• extend hpdcache (high performance data cache) so that it can also serve as an instruction cache
• cf. https://github.com/openhwgroup/cv-hpdcache/pull/16

detail

• axi arbiter for extended hpdc

HOW to extend hpdcache

• High Performance Instruction Cache:
  • instruction cache with 3-stage pipeline, Replay Table and MSHR
  • based on the original hpdcache code, remove the module for the write buffer part and the signals that control it, plus the module for the uncacheable write part and the signals that control it
  • the depth of Replay Table and MSHR will be decided through performance evaluation (reason: The utilization of the instruction cache is dependent on the capability of instruction fetch.)
• replace current cva6_icache in cva6_hpdcache_subsystem.sv by High Performance Instruction Cache
  • arrange cva6_hpdcache_subsystem_axi_arbiter so that the interface will be appropriate

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[MikeOpenHWGroup]

Thanks for the contribution @takeshiho0531! I have left a few comments and will leave it to other members of the team to review/approve this PR.

In addition to the specific comments, it would be very good indeed if you could provide a markdown (rst) file documenting how you have extend hpdcache so that it can be used as an I$.

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[JeanRochCoulon]

@takeshiho0531 THis PR is open for a while. What is his status? If not needed for cva6 project, please close it.