cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Hi, while verifying access modes for PMPADDR CSR I am facing issues on spike configuration as mentioned below. As CVA6 core has a granularity of 8 bytes that bit-0 of...
Modify the DvPlan according to changes in the AXI user guide
Modify AXI interface specification by adding constraint that are not supported by CVA6
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When performing floating-point division using the `fdiv.d` instruction in...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In some rounding mode, precision errors occur when calculating...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When executing the `fsqrt.d` instruction on a double-precision floating-point...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, After running a rest CSR test, I observe...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Description** I have encountered a bug where the NX...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description EDIT: The CVA6 can access an address beyond the...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, In the RISCV spec section 3.7 Physical Memory...