cva6

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Spike: FS field is not configurable [SSTATUS CSR is failing while verifying Access mode]

4

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description While verifying Access mode for SSTATUS CSR test is...

spidugu444

[BUG] <Wrong assignment of X_NUM_RS>

6

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, I notice that in the cvxif.pkg, the **X_NUM_RS**...

AyoubJalali

Co-simulation mismatch when reading stval CSR

2

### To reproduce This failure happens when running one of the riscv-isa tests: `rv64ui-v-bltu`. ```c make verilate DROMAJO=1 make run-dromajo-verilator BIN=$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-v-bltu ``` ### Details According to ISA spec (from what...

kabylkas

Incomplete information on SATP CSR's ASID field

3

Hi, As per RISCV privileged specification ASID field in SATP CSR is dependent on RTL implementation, could anyone please let me know what will be the RTL implemented value for...

spidugu444

A corner case in std_dcache when executing AMO instruction

1

Hello, We find a corner case associated with std_dcache and AMO/ld instruction, which makes Linux crash. It is caused by the interface signal miss_req between cache_ctrl and miss_handler in std_nbdcache....

timingwalker

Floating point multipication issue in RISCV cva6

4

Hi All, In CVA6 riscv-arch-test suite fmul tests are failing due to incorrect calculation as shown in below attached screenshot.  As shown in above in line 157 and 182...

spidugu444

A corner case in std_icache when kill_s2 is asserted

6

Hello, We find a corner case associated with BranchPrediction/std_icache/PTW when we try to boot the Linux OS with std_cache_subsystem. An error address translation result is returned by PTW，which makes the...

timingwalker

MMU: INSTR_ACCESS_FAULT triggered by PMP

3

In mmu.sv, line 247, there's a mixture of vaddr and PLEN, which causes a misalignment in `tval` ```icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, icache_areq_i.fetch_vaddr}, 1'b1};``` Same for line 258 ```else icache_areq_o.fetch_exception =...

masgia

[BUG] Failure of AXI atomic transaction

2

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In case of an AXI atomic transaction, the CVA6...

Ohouti

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description There are four different cases of `sfence.vma` that are...

fatimasaleem