cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, this issue is about the **RVFI** tracer that...
### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Currently, the Github CI utillizes the Makefile directly with...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Last month, I successfully booted and ran linux system...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description See #1272 for further explanations
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I utilize the "make fpga" command to generate .mcs...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description On page A3-45 (AXI3 write transaction dependencies), the [AXI...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description While verifying Access mode for MIP(Machine Interrupt Pending) CSR...
Three issues have been encountered while verifying the access mode behaviour of the PMP CSRs. 1. PMPADDR[8]- PMPADDR[15] : read zero after writing it with non-zero value. 2. PMPCFG[0]- PMPCFG[1]...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description The master can know the status of a transaction...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I believe there may be a problem with the...