cva6
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openhwgroup
[TASK] Add CSRs and MEM read info to CVA6 RVFI
Background
CSR state information (either full state or change sets) is necessary to verify the RTL behavior against the Reference Model (the Spike ISS). In mainline Spike the CSR state information is reported using change sets (sets of register commits).
What (objective description)
Provide CSR state information in th RVFI interface of CVA6 RTL.
How To
- Extend the definition of the RVFI interface with CSR state (or CSR state change) signals.
- Propagate all CSR values effective at instruction commit / exception raise time to the RVFI interface.
Current Status
TODO
Risks
Size of the full state wire set may impact RTL simulation performance.
Prerequisites
None
KPI
TBD (simulation slowdown threshold?)
Description of DONE
Tandem simulation using RTL and Spike supports comparison of CSR values between RTL and Spike upon all CSR state changes occurring when execution CI tests.
This task supersedes #1362.
As @MikeOpenHWGroup commented in #1362,
I recommend that we implement the RVFI tracer to the same specification as is used by the CV32E40S core. This is an extension of the original RVFI-specification from SymbioticEDA.
Furthermore, we should also consider implementing the CVA6 RVFI as behavioral code that will not be synthesized into gates. This will save a very large number of I/O on the top-level of the core. A good example of how this is done is in the cv32e40s wrapper.
It is also worth considering the RVVI-Trace, an extension of the RVFI proposed by Imperas. The best thing about RVVI is that it provides a nice set of timing diagrams to define the interface's operation in specific corner cases.
