CVA6 Makefile sets random seed to "1"

[MikeOpenHWGroup]

The Makefile at core-v-verif/cva6/sim/Makefile "hardwires" the random seed:

ALL_SIMV_UVM_FLAGS      = -licwait 20 -l +ntb_random_seed=1 \

I see that core-v-verif/cva6/sim/cva6-simulator.yaml appears to offer the ability to override this:

<out>/vcs_simv +vcs+lic+wait gen="true" <sim_opts> +ntb_random_seed=<seed> <cov_opts>

How does this work? Once the Makefile sets +ntb_random_seed to "1", can it be over-ridden by the configuration in the yaml?

[AyoubJalali]

Hello @MikeOpenHWGroup indeed +ntb_random_seed it override but not by core-v-verif/cva6/sim/cva6-simulator.yaml, it's the --sv_seed option in verif/sim/cva6.py