cva6

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[Spike] : unsupported unprivileged counters CSRs : cycle[h], instret[h]

4

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Spike don't support unprivileged counters CSRs, as cycle[h], instret[h]....

AyoubJalali

Spike : Unrecognized CSR

3

Hello, As i know the ICACHE_CSR is implemented in the STEP1 configuration, so i generate a test with a csr instruction with ICACHE_CSR = 12'b700, the spike model raised an...

AyoubJalali

[TASK] Compare Spike and RTL in tandem

9

**Background** Lockstep ("tandem") co-simulation allows early detection of divergences between behaviors of different simulation models on the same test case. Typically, an Instruction Set Simulator (ISS) and an RTL simulator...

zchamski

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In the [CSR embedded doc list](https://gitlab-tss.gemalto.com/riscv/ohg-pr/cva6/-/blob/9952bce6a61faa8a0c3a25e72526f0d57cb699eb/docs/csr-from-ip-xact/embedded/cva6_csr.md), there is a...

AyoubJalali

[BUG] ASIC synthesis failed related to ariane_pkg.sv

3

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, I am trying to implement the CVA6 on...

andriami

[BUG] No documentation on CVA 6 Boot Process

1

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I need help understanding the CVA6 boot process -...

rajatkmitra

[TASK] Prepare documentation of multiple CVA6 variants

1

### Task Description #1691 plans to document several variants of the CVA6. This is a big piece of work. To make this work easier, some preparation is needed first: -...

cathales

[TASK] generate documentation (User Manual and Design Documentation) with templating

3

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Several cva6 configurations must co-exit in documentations Templating will...

JeanRochCoulon

Read, Write & Execution on 0x0 address

3

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, So I notice that the CVA6 has permission...

AyoubJalali

[TASK] Modify Spike to match core-specific configuration

12

**Background** Spike implements a complete set of functionality corresponding to the RISC-V specifications. At times this set can be a superset of features of an implementation, in particular in the...

zchamski