MIP CSR is failing while verifying access mode

[spidugu444]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

While verifying Access mode for MIP(Machine Interrupt Pending) CSR on CVA6 core, test got failed on RTL end due to the default reset value as it is reading as 0x00000080. As per riscv priviliged specification default reset value for MIP CSR is 0x00000000.

For quick reference please find attached log files. riscv_vcs_mip_csr_test_0.log riscv_spike_mip_csr_test_0.log

Note: on spike end test is working fine.

[MikeOpenHWGroup]

Hi @frikhaAziz, can you have a look at this one?

[MikeOpenHWGroup]

Hi @ASintzoff. @JeanRochCoulon let me know that @frikhaAziz has completed his internship, so I am assigning this one to you.

[ASintzoff]

CSR mip: 0x00000080 => bit 7 (mip.MTIP) is set