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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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I'm new to CVA6, but I can't use CVA6.py to run a cpp file(by using GCC Toolchain built following the Quick setup).Can someone provide me with certain instructions to help?I...

Type:Question

Hi, I am getting an error inside **printf** function of verif/tests/custom/common/syscall.c as > /home/kinzah/Documents/cva6/verif/sim/../tests/custom/common/syscalls.c:405:(.text+0xf64): undefined reference to `__riscv_flush_icache' > collect2: error: ld returned 1 exit status The command ran was...

Type:Bug

Unification of MMU sv32, sv39 and sv39x4

Change the current Github CI to use `cva6.py`

This MR content 2 commits : 1. Connect CSRs info coming from RVFI (implamanted recently by @ycasamat) in the testbench 2. Update target simulation (use CV32A65X)

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, I am trying to generate waveform in Verilator...

Type:Bug

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Issue #1300 should be fixed by PR #1719. There...

Type:Task
notCV32A65X

Zcmp ExtensionIntroductionThis PR is adding a set of instructions(cm.push, cm.pop, cm.popret, cm.popretz, cm.mvsa01, and cm.mva01s) that may be executed as a series of existing 32-bit RISC-V instructions. The objective is...

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description We are currently porting the verification to be compliant...

Type:Bug

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description The GCC toolchain builder "Getting Started" instructions: * https://github.com/openhwgroup/cva6/tree/master/util/gcc-toolchain-builder#getting-started...

Type:Bug