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openhwgroup
[TASK] Add a test for misaligned branches
Is there an existing CVA6 task for this?
- [X] I have searched the existing task issues
Task Description
Issue #1300 should be fixed by PR #1719. There is no regression, but we lack a test to verify that the bug is actually fixed. (With TDD we would have added this test before fixing the bug)
Required Changes
Add a test branching to a target_address such as target_address[1:0] is 2’b10.
A misaligned address exception shall be raised if RVC extension is disabled, but not if RVC extension is enabled.
@AyoubJalali Can you tell me whether this test should be linked to ISACOV ? Is it possible to generate it with riscv-dv ?
👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
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👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
@AyoubJalali Any idea ?
we can't raise this exception, because we support C extension, so it means that we should Execute on an address half-work misaligned LSB bit != 0 -> and this can't never happen in the RISC-V architecture because The jump and branch interuction always clear the LSB bit
As it is not 65x, we keep the github issu eopen but I change the assignee