cva6

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Generate separate per-target logs when simulating.

1

* verif/sim/Makefile (veri-testharness): Don't add target name to waveform file name. (vcs-uvm): Ditto. * verif/sim/cva6.py (run_assembly): Add target name to log file name. (run_elf): Ditto. (run_c): Ditto. (iss_sim): Ditto. (iss_cmp):...

zchamski

Improve environment setup. Fix Verilator installation process.

2

* verif/sim/setup-env.sh: Double-quote variable values. Install Verilator in 'tools/verilator' by default. Add SPIKE_PATH to PATH. * verif/regress/install-verilator.sh: By default use per-version dirs to build and install Verilator. Add and improve...

zchamski

On scripts and management of source files

3

I aim to include an accelerator as part of the cva6 application processing unit. I plan to use Verilator for simulation and Vivado for synthesis. To this end, I have...

Juan-Gg

[BUG] Instruction are incomplete

22

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Seems like the cva6 home page was updates (removed...

rajatkmitra

[Xcelium support] Remove void from DPI definition

2

This PR is related to the one done on core-v-verif with the same subject: https://github.com/openhwgroup/core-v-verif/pull/2366 Since the definition of the function `read_section_sv` has been updated in core-v-verif, its import needs...

CoralieAllioux

Draft: User config

6

> :warning: This PR is not ready for merge yet. It builds CVA6 with embedded configuration on Verilator and runs CoreMark but there are still formatting + history cleanup +...

cathales

Rework syscalls.c once system prints are implemented

2

[#1857](https://github.com/openhwgroup/core-v-verif/pull/1857/files#diff-62f67c1d16e0eb8da38c8838b66b69e31890c555b9d2ad5509d245754da1f25d) introduced two new functions: https://github.com/openhwgroup/core-v-verif/blob/1eac965d073abc18ab6aff5e6f62fd635b060746/cva6/tests/custom/common/syscalls.c#L78-L81 and https://github.com/openhwgroup/core-v-verif/blob/1eac965d073abc18ab6aff5e6f62fd635b060746/cva6/tests/custom/common/syscalls.c#L164-L173 We might want to move or modify them once system prints is made via UART both in Spike and CVA6. (Related: openhwgroup/cva6#1421)

cathales

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description We are currently porting the verification to be compliant...

CoralieAllioux

[TASK] Add extension and features tags on tests in testlists

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### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Add tags on tests in testlists to identify extension...

Gchauvon

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Support additional simulator: Cadence xcelium. The support concerns uvm...

CoralieAllioux