rohd
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intel
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
### Describe the bug The generated SV for assigning an unpacked array port to a packed array port in the parent module causes a direct connection. For example: ```SystemVerilog module...
### Motivation People may want to compile ROHD into WASM (https://dart.dev/web/wasm). Note that the "WASM compatibility" score will be affected in the future on pub.dev: https://pub.dev/packages/rohd/score We already have javascript...
### Motivation Sometimes there are assignments between a `LogicArray` with 1 dimension (packed), and a `Logic` of the same width. It would be nice to generate that SystemVerilog as a...
### Motivation For some types of operations, one may wish to use the result of an operation as either a driver or a receiver. A common example would be swizzles...
### Motivation It would be nice to mark the bit positions/ranges in swizzles so that the SystemVerilog could become more readable. For example: ```SystemVerilog assign my_swizzle = { c, //...
### Motivation Information about the original Dart source code that generates some output (e.g. SystemVerilog) could theoretically be extracted during construction and annotated in the result, for example using `StackTrace`....
### Motivation If a top-level module has it's `build` called after some sub-modules have already called `build` separately, then you may get an error like the `ModuleNotBuiltException` when running it...
### Motivation It's legal in SystemVerilog for an assignment to be a swizzle: ```SystemVerilog assign {a, b} = {c, d}; ``` Currently ROHD will create an intermediate signal for logic...