Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle

[mkorbel1]

trafficstars

Motivation

Sometimes there are assignments between a LogicArray with 1 dimension (packed), and a Logic of the same width. It would be nice to generate that SystemVerilog as a simple assignment instead of first going through a swizzle conversion.

Desired solution

Somehow transform assignments in generated SystemVerilog to avoid unnecessary swizzling prior to assignments between 1-D packed LogicArrays and Logics.

Alternatives considered

No response

Additional details

No response