rohd
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intel
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
### Motivation Usually, if someone calls `Simulator.run` and there are no registered events in the simulator, that would be a bug. It would be nice to either throw or at...
## Description & Motivation There are often questions about trusting ROHD simulation and SV generation, so this PR adds documentation around that to the user guide. Also in this PR...
## Description & Motivation This PR has a handful of upgrades to `FiniteStateMachine`s so that it is easier to construct and generate readable FSM code. - Add labels in generated...
### Motivation We often have Enums as constant integers that also need to be used as Const Logic. While we can call the index of the enum, we lose its...
### Motivation When dealing with known-radix strings for IO, it would be useful to not have to prefix (say in wave displays or table displays, or for debug alignment). For...
### Motivation If someone, for example, calls a `swizzle` on a bus but doesn't use the output, the result still shows up in the SystemVerilog. This isn't functionally necessary, and...
### Motivation The `flop` function and `FlipFlop` module flatten structures and arrays to a single packed `Logic`. If you want to flop an array or a structure, you may often...
### Motivation I want to be able to correlate my input ROHD and output Verilog and track changes. The timestamp clutters up my diff. ### Desired solution An option on...
### Describe the bug This gives an error: ``` Error: Undefined name 'MyStruct'. MyStruct._(Logic(name: 'ready'), Logic(name: 'valid')); ^^^^^^^^ ``` ```dart class ReadyValidStruct extends LogicStructure { final Logic ready; final Logic...
### Motivation These functions have been super useful. Can they be showcased in the User Guide? ### Desired solution User guide includes documentation and examples for these automations. ### Alternatives...