rohd

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`Logic.zeroExtend` should return `this` if `width` is the same as `newWidth`, and `Swizzle` optimization in SV generation

1

### Describe the bug When zero-extending a signal, if there's nothing to zero-extend, we can just immediately return `this` rather than go through a `Swizzle`. Additionally, when `Swizzle` gets only...

mkorbel1

Add helper function(s) to "split" `Logic`s and `LogicValue`s

2

### Motivation Some common use cases: - Split a bus into individual bits to be processed independently - Split a bus into chunks of equal size (e.g. bytes) - Split...

mkorbel1

Pipeline must provide access to inputs of a given stage.

6

### Describe the bug The Pipeline abstraction only provides an API to get the combinational version of a pipeline signal in a given stage. Hence, if you want to do...

kimmeljo

### Motivation Edalize is a library that helps interact with various EDA tools https://github.com/olofk/edalize It would be nice to add capabilities to ROHD to generate inputs to edalize to make...

mkorbel1

### Motivation Sometimes there's a bunch of different independent hierarchies that we want to generate SystemVerilog for. If we generate them with independent `SynthBuilder`s, then any shared sub-modules may be...

mkorbel1

### Motivation When you add a sub-interface to a `PairInterface`, then if you ever use `receiveAll` or `driveAll`, it won't apply to all the `subInterfaces`. It would be nice if...

mkorbel1

Add capability to `PairInterface` to modify naming at time of `addSubInterface`

1

### Motivation The option to expose `modify` is up to the constructor of an interface extending `PairInterface`, but at the time of adding a sub-interface is likely a point where...

mkorbel1

### Motivation A lot of the time, someone may want to instantiate a SystemVerilog module without creating a new class definition or defining any internal behaviors. In these cases, you...

mkorbel1

The documentation for instantiating other things in SystemVerilog is not clear enough and could really use some examples. https://intel.github.io/rohd-website/docs/external-modules/ It would be nice to cover: - `ExternalSystemVerilogModule` - `CustomSystemVerilog` -...

mkorbel1

Simulator optimization: don't simulate signals that don't matter (optionally)

1

### Motivation Much of the time, only signals that are actively being listened to or outputs of a module are the only things that matter for an accurate functional simulation....

mkorbel1