rohd

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## Motivation "It's cumbersome and error prone to have to keep resetting flops I'm adding" When creating lots of flops in a `Sequential`, often you want them all reset by...

mkorbel1

Create something like a `LogicStructure` to group `Logic`s in a way that can be used like `Logic`

4

**Is your feature request related to a problem? Please describe.** Similar to the ability to treat structs as signals in SystemVerilog. **Describe the solution you'd like** The `LogicStructure` object would...

mkorbel1

## Motivation Many of the gates have input port names like `a` and `b` and output ports like `y`. It would be great to name these something better. ## Desired...

mkorbel1

## Motivation Uniquification in hardware is a common problem, and exporting the `Uniquifier` implementation in ROHD can be helpful to others. `SimCompare` has some useful utilities that might be helpful...

mkorbel1

## Motivation It's annoying and confusing to need to set the `signalToWidth` map for `SimCompare` after already setting port widths properly. ## Desired solution Remove the `signalToWidthMap` from `SimCompare.iverilogVector`, and...

mkorbel1

Provide an easy method for adding comments to generated outputs

1

## Motivation Some users of ROHD are interested in adding comments to the generated output SystemVerilog to improve readability, debuggability, and traceability for complex generation flows. While it's possible to...

mkorbel1

More complete support for signed operations

3

## Motivation Right now most operations in ROHD are unsigned. Less than, greater than, etc. would be a lot more convenient with some built in signed support. ## Desired solution...

mkorbel1

Make `LogicValue` `toInt`, `toBigInt`, etc. return `null` when signal is invalid instead of an Exception

3

## Motivation Dealing with null is easier with Dart's null safety than an exception. ## Desired solution Functions that might not have a valid int/BigInt representation due to invalid signal...

mkorbel1

Zero width signals get created as 1 bit signals in generated SystemVerilog

1

## Describe the bug Zero width signals get created as 1 bit signals in generated SystemVerilog ## To Reproduce Make a zero-bit port for a module and generate the SystemVerilog...

mkorbel1

Add support to "name" `Pipeline` stages and reference them by name

2

## Motivation Different stages of a pipeline may have meaningful names associated with them, and logic from within or outside the pipeline may want to access a certain stage's signal...

mkorbel1