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The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

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### Motivation There are some cases where the top of the module definition may need to be modified slightly, but not entirely. For example, adding package imports (in case they...

enhancement

### Motivation There are scenarios where it's convenient to use a `List`, especially as an argument to functions or constructors for modules. Keeping it as a `List` requires iterating through...

enhancement
good first issue

### Motivation There are some things in ROHD that can be a bit verbose/redundant. For example, a simple port whose variable name and String port name are the same, and...

enhancement

### Motivation In SystemVerilog and some other HDLs/generator frameworks (e.g. Chisel) there are APIs for assigning an element/range of a bus/array where the index is itself a signal. This implies...

enhancement
help wanted

### Motivation The "port" style constructors include: ``` Logic --> Port LogicArray --> LogicArray.port LogicNet --> LogicNet.port LogicArray.net --> LogicArray.netPort ``` One of these is not like the others. Moving...

enhancement

### Motivation Often there is a "default" value that would be desirable for most states in a `FiniteStateMachine`, but the current implementation requires repeating the same default across all states...

enhancement
help wanted

### Motivation There are multiple places across ROHD and ROHD-HCL where public and private implementations of some common math operations are included. For example: - `LogicValue` has `clog2` - `FiniteStateMachine`...

enhancement

### Motivation It can be useful to generate SystemVerilog that has more context than just bare signals and arrays. For example, a struct instead of a bunch of independent signals,...

enhancement

## Description & Motivation For ROHD classes which use begin/end to define blocks in generated SystemVerilog, support tagging the block with an optional label. This is helpful to generate SystemVerilog...

### Describe the bug The `execute` function should be `@protected` in all `Conditional` objects, only called by `Always` execution. Some of them are missing and should be added so that...

bug