Allow swizzles to be receivers of assignments in generated SystemVerilog for nets

[mkorbel1]

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Motivation

It's legal in SystemVerilog for an assignment to be a swizzle:

assign {a, b} = {c, d};

Currently ROHD will create an intermediate signal for logic nets, rather than do it in a single net_connect line.

Desired solution

Enable the ROHD SystemVerilog generation to merge assignments between swizzles.

Alternatives considered

No response

Additional details

No response