Mark bit ranges in swizzles in generated SystemVerilog

[mkorbel1]

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Motivation

It would be nice to mark the bit positions/ranges in swizzles so that the SystemVerilog could become more readable. For example:

assign my_swizzle = {
  c, // 4:2
  b, // 1
  a  // 0
};

Desired solution

When generating the output of a Swizzle, mark the bit positions with comments to make the SV more readable

Alternatives considered

No response

Additional details

No response