rohd
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intel
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
### Motivation Sometimes it would be nice to be able to transpose an array. There may be other utilities as well worth adding. ### Desired solution Add utilities like transpose...
### Motivation Add a simple example to website https://intel.github.io/rohd-website/docs/logic-arrays/ on how to use array assignment, users are confuse with: ```dart logicArray.elements[0]; // a[0] ``` Probably, example of assignment in conditionals...
## Description & Motivation Updating to use a new type of self-hosted runner for GitHub actions. This should help with the slow pick-up of jobs from the GitHub-hosted runners. This...
### Motivation In addition to #69, it would be nice to be able to use an async reset on the flop. ### Desired solution Add a way to configure the...
### Motivation The `ReadyValidPipeline` currently hijacks access to `stall` signals. This is annoying if you want to stall pipeline stages for other purposes than just backpressure on the end of...
### Motivation The `SimCompare` utility generates messages like "expected y=1'bx but found..." in the generated SV testbenches. This is inaccurate for multi-bit invalid signals. This is not a functional problem,...
### Motivation See https://github.com/intel/rohd/discussions/363 It might be nice to assign part of a signal conditionally. ### Desired solution A function on `Logic` which could do a partial set (maybe similar...
### Motivation There are known bugs with "unpacked" arrays in SystemVerilog. For example: - Assigning: - - - Single-element unpacked: - The ROHD test-suite relies on SystemVerilog simulators to verify...
### Motivation Many repos have code coverage metrics provided in two places automatically: - On the README as a badge, indicating coverage for the repo by the test suite. -...
### Motivation The presence of internal signals in the `WaveDumper` output can interfere with black box debugging (when only input/output ports is evaluated). ### Desired solution Add the ability to...
