Add optional source annotation in generated outputs

[mkorbel1]

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Motivation

Information about the original Dart source code that generates some output (e.g. SystemVerilog) could theoretically be extracted during construction and annotated in the result, for example using StackTrace. This type of information could be valuable for debug and mapping of generated outputs back to their original ROHD representation.

Desired solution

Add a way to annotate generated outputs with the original source code line in Dart.

Alternatives considered

No response

Additional details

The StackTrace functionality in Dart should be helpful here, but it might be tricky to figure out which lines in a trace are useful/relevant and which trace is most relevant to a generated line of verilog, since many pieces of code may contribute.