rohd

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Omit redundant parentheses in generated SystemVerilog

2

### Motivation There are a handful of cases where generated SystemVerilog has too many parentheses. Currently, they are added conservatively for safety, to ensure order of operations and evaluation matches...

mkorbel1

WaveDumper outputs empty file when test() {expect()} fails

1

### Describe the bug I am using the test() { expect () } construct and when the expect throws an exception the resulting wave.vcd is empty. Would be nice to...

awmoore-intel

Waveform shows 'x' when driving signal with 'z'

2

### Describe the bug RTL Output correctly shows z's being assigned, but waveform shows X's. Seems like waveform only shows z's when a signal not driven. ``` // combinational always_comb...

awmoore-intel

Improve error message of `Signal changed its value after ...`

5

### Motivation I am getting this error message but have no idea what signal has the issue. ``` Signal changed its value after being used within one `Combinational` execution. This...

awmoore-intel

### Motivation Based on discussion in #569 It can be useful to use `Combinational.ssa` in a `FiniteStateMachine`, but there's not really a way to do that currently. ### Desired solution...

mkorbel1

### Motivation The user guide page for external modules is a little thin: https://intel.github.io/rohd-website/docs/external-modules/ An example would be really helpful! ### Desired solution Add an example to the documentation (doc/user_guide/_docs/A17-external-modules.md)...

mkorbel1

SimpleClockGenerator doesnt work with period of 1

1

### Describe the bug Listening on a posedge of the clock when clock period is 1 loops forever but never advances time. I'm thinking 1 is not allowed? Perhaps throw...

awmoore-intel

### Motivation If you're not careful, it's possible to generate really really long names for signals in generated outputs (e.g. SystemVerilog). For example, if you use lots of & gates,...

mkorbel1

Automatic sorting and grouping for generated outputs

1

### Motivation Currently, the order of module and signal declaration within generated outputs can appear somewhat random, being largely dependent on the order of construction and parsing. There may be...

mkorbel1

### Motivation Currently, if a port has a dangling port, the instantiation in generated verilog will create a `logic` to put on that port, then leave it floating. It would...

mkorbel1