rohd
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intel
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
### Motivation In #475, some changes were proposed to the simulator that modified how injected actions were executed. The existing test suite in ROHD did not identify any problems, but...
## Description & Motivation See #444 ## Related Issue(s) Fix #444 ## Testing ## Backwards-compatibility > Is this a breaking change that will not be backwards-compatible? If yes, how so?...
### Describe the bug The `uniquify` function in `Interface.connectIO` is supposed to apply to all ports, but there is missing logic to handle uniquification for `LogicArray`s. ### To Reproduce _No...
### Describe the bug The `PairInterface` is supposed to be easier to declare ports via the constructor arguments, but it accepts `List` which notably does not allow for `LogicArray`s. ###...
## Description & Motivation Even though SystemVerilog parameters are not supported for controlling anything within generated outputs of SystemVerilog, sometimes there is a need to pass parameters down through a...
### Motivation VHDL is a popular alternative to SystemVerilog ### Desired solution The capability to generate VHDL in addition to SystemVerilog, as well as instantiate external VHDL modules instead of...
### Describe the bug The assertion is: if (receiver.parentModule != module && !module.subModules.contains(receiver.parentModule)) { // This should never happen! assert(false, 'Receiver is not in this module or a submodule.'); continue;...
### Motivation Currently, `Const` is just a `Logic` that initializes itself with a specific value. Technically, the value could be changed later via a `put` directly on the `Const` or...
### Describe the bug For example, when shifting by an integer (e.g. `
### Motivation There's currently no way to swizzle or grab a subset of a `LogicNet` (or similarly array net) and have the result also be a net that is capable...