cva6

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Ariane bitstream generation issue

1

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description hajra@merledu1:~/ariane$ make fpga make -C corev_apu/fpga/src/bootrom BOARD=genesys2 XLEN=64 bootrom_64.sv...

HajraKamran

fpga: bootrom: Fix definition and declaration mismatch of function

3

Fixes compile errors in newer gcc versions, I observed it with version 15.1.0: ```C src/main.c: In function 'main': src/main.c:52:5: error: too many arguments to function 'init_uart'; expected 0, have 2...

akorb

OpenOCD: Update config syntax

2

Update OpenOCD Config files to remove deprecated syntax. This stops error messages such as: ```bash DEPRECATED! use 'adapter speed' not 'adapter_khz' DEPRECATED! use 'adapter driver' not 'interface' DEPRECATED! use 'ftdi...

RoanR

CVA6 interconnect ports is now available in two versions: - Single AXI interface, with cache I and D (Icache/HPDCache) - 5 OBI interfaces - without any caches in the CVA6...

yanicasa

Open-source (yosys) synthesis of CVA6 (possible ?)

27

I am aware of PULP Platform's [pulp-platform/croc](https://github.com/pulp-platform/croc.git) and [pulp-platform/cheshire](https://github.com/pulp-platform/cheshire.git) that support Yosys. Croc is a tiny RISC-V chip for educational purposes, whereas Cheshire is a SoC with CVA6 sitting at...

isa084

Illegal instruction handling

1

I'm getting some odd errors in `mtval` with certain illegal instructions. `mtval` (when enabled) should be reported as the illegal instruction bits for all illegal instructions. However, for the illegal...

PRugg-Cap

### Is there an existing CVA6 bug for this? - [x] I have searched the existing bug issues ### Bug Description Further to https://github.com/openhwgroup/cva6/issues/3018, the following TVAL behaviours currently in...

PRugg-Cap

Currently TVAL is reported as the address of the branch itself on a branch/jump misaligned instruction (redundant with EPC). https://github.com/openhwgroup/cva6/blob/301d11ceb88c1169f75e9dea415e4bff4eb29888/core/branch_unit.sv#L123 From the RISC-V privilege spec, it should be the "faulting...

PRugg-Cap

Modifying the selected ISA extensions

1

I'd like to modify the selected extensions, but they seem to be referenced in multiple files. Could you clarify if there is a script that we can use for this?...

ellial

Add ALU to ALU bypass in superscalar mode

32

This PR introduce ALU to ALU bypass to allow dual issue of consecutive ALU instructions with a RAW dependency. The ALUs are now instantiated inside a wrapper module, which provides...

ricted98