cva6

cva6 copied to clipboard

build(deps): bump verif/core-v-verif from `60e5724` to `65593a9`

1

Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif) from `60e5724` to `65593a9`. Commits 65593a9 Merge pull request #2622 from ThalesSiliconSecurity/obi_data_width 7c64f11 OBI assert : Support DATA_WIDTH=64 for R-8 assertion 2282464 Hotfix to fix security vulnerability a0214e2...

dependabot[bot]

[BUG] List index out of range error for performance model

3

### Is there an existing CVA6 bug for this? - [x] I have searched the existing bug issues ### Bug Description When executing python3 perf-model/model.py verif/sim//spike_sim/hello_world.rv32imc.log (or any other core...

ellial

[hpdcache] Simulation time out - suspected hpdcache config bug

4

I encountered an issue while running a basic hello_world test using the `cv64a60ax_config_pkg` configuration of the CVA6. Relevant parameters are: ``` AxiDataWidth = 128 DcacheLineWidth = 512 ``` The test...

IhsaneTahir

[ptw bug] shared_tlb_update_o has connnection issue with g_content (RVH enable)

4

Hi @AngelaGonzalezMarino There seems to be an issue in the PTW code at this line https://github.com/openhwgroup/cva6/blob/a9190fde99b7adf14b74b0b56ff6f47ccce5f1f9/core/cva6_mmu/cva6_ptw.sv#L210C7-L210C26 shared_tlb_update_o.content = gpte_q | (global_mapping_q

khandelwaltanuj

[DO NOT MERGE] docs: Review of the current cv32a60x documentation

4

DO NOT MERGE! Hi @ASintzoff and @MikeOpenHWGroup , I analysed the docs under https://cva6-cv32a60x.readthedocs.io/en/latest/07_cv32a60x/, the parts that are specific to the CV32A60X, I would like to point out some questions...

cairo-caplan

Document how to load and run zephyr RTOS

4

Starting with the upcoming release 4.2.0 (and the current main branch), the zephyr RTOS has support for running on the 32/64 bit configurations of cva6 on the Genesys2 board. This...

WorldofJARcraft

Hi all, This is a question rather than an issue - please direct me if I'm asking it in the wrong place! I am considering using CVA6 in research focused...

Chrisdb1

[mmu shared tlb] index of a set seems to be extracted from VPN0 even in the case of superpage ?

2

Hello, I have a question regarding how an index of a set is calculated in the case of a superpage. It seems to use the bits [$clog2(SharedTlbDepth) -1: 0] of...

khandelwaltanuj

Problems when simulating multiple .c files

3

I want to simulate an XTS-AES implementation in C on the CV32A65X. I followed the entire tutorial and used the supplied commands to build the RISC-V toolchain. Everything worked without...

Rocketuser01

[mmu question] Is it ok for the tlb_flush/flush to arrive during an ongoing translation ?

7

Hello I have a question regarding the flush of MMU. In my UVM TB tlb_flush and flush may arrive anytime randomly. I get a feeling that when a tlb_flush arrives...

khandelwaltanuj