cva6
cva6 copied to clipboard
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters). As of now, they are committed to the repository and can be out of sync...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When I synthesize cva6 with WB cache, there is...
Hi I want to implement a new instruction, but I can't find a clear explanation of how to do it. Is there any guide on how to add a custom...
This adds a tutorial on how to customise the example coprocessor with your own instructions and test them.
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, RVFI agent + spike Tandem is degrading considerably...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description The top-level `README.md` contains broken links: * [Build Status](https://camo.githubusercontent.com/9ff2dee66f99859e54fc00ae12337b369257f9a946c2cccf79961d5ae46aee6c/68747470733a2f2f72697363762d63692e70616765732e7468616c65732d696e7669612e66722f64617368626f6172642f)...
The assertion included in the `always_comb` block apparently violates the requirements in [section 9.2.2.2.2 of the SystemVerilog standard](https://ieeexplore.ieee.org/document/10458102): > Statements in an always_comb shall not include those that block, have...
### Is there an existing CVA6 bug for this? - [x] I have searched the existing bug issues ### Bug Description According to [CV32A65X Spec](https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/riscv/priv.html#_machine_interrupt_mip_and_mie_registers), `As the system has only...
Hello guys, Currently the spike tandem is working only with the configuration of CV32A65X, i want to ask what i need to do in the spike.yaml file if i want...