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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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Update the HPDcache submodule into CVA6

Component:RTL

Using the MMMPID to show version of the core code is useful

This pull request introduces support for RISC-V proxy kernel into veri-testharness simulation target. It is a follow up to the discussion in https://github.com/openhwgroup/cva6/issues/2426 Highlights : 1. Successfully tested with cv64a6_imafdc_sv39,...

Simple addition to prevent errors in the smoke test scripts not being reported.

The HPDcache requires that the refillFIFO (inside the miss handler of the HPDcache) buffers at least an entire cacheline. For this reason, its depth needs to be computed according to...

# CV32A60X TRL5 Branch Integration — Work in Progress ## 🚧 Current Status: Merging TRL5 Branch into MASTER We are actively working on merging the **cv32a60x** branch into the `master`...

More testing in real conditions pinpointed some bugs: * `iretire` value was sometimes off by 1 because `counter_o` was not cleared correctly in instr_to_trace * A dimension was redundant in...

Bumps [core/cache_subsystem/hpdcache](https://github.com/openhwgroup/cv-hpdcache) from `04de808` to `882aba1`. Commits 882aba1 uc: fix missing async reset value 0afd6dc README: add synthesis directory description e8d64f9 syn: add support for Yosys synthesis for area estimation...

dependencies
submodules

I modified `include/build_config_pkg.sv` and `include/cv64a6_imafdc_sv39_config_pkg.sv` to enable Superscalar mode and a six-port register file. I then ran [smoke-tests-cv64a6_imafdc_sv39.sh](https://github.com/openhwgroup/cva6/blob/master/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh) The assembly programs ran fine, but the smoke test failed on hello...

As far as I can see the only difference between `tc_sram_wrapper_cache_techno` and `tc_sram_wrapper` is that is adds `BYTE_ACCESS` which presumably communicates down if byte-enable is required. Otherwise it looks to...