cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
This PR contains the necessary updates to run Questasim (version: 2023.2) for CVA6.
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I get the following output on the command line...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello guys, I am trying to simulate cva6 with...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When I synthesize cv64a6 core with `cv64a6_imafdc_sv39_config_pkg.sv` with Design...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, I am facing issue in make file of...
Bumps [core/cache_subsystem/hpdcache](https://github.com/openhwgroup/cv-hpdcache) from `b4519e7` to `e33209c`. Commits e33209c Update the CHANGELOG 85a693a docs: update to describe hybrid write-policy feature e58b4aa pkg: remove obsolete wbufSendFeedThrough config parameter 035bf61 tb: add single...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In setup-env.sh line 45, VERILATOR_INSTALL_DIR is set to "$ROOT_PROJECT"/tools/verilator...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In RISC-V, jumps to misaligned instruction addresses should trigger...
Extraction of the PMP outside of the MMU. Replacement of PR2476
Hi, I was testing the AMO instructions. I observed that in the axi adapter, communication on AW and W channels are being carried out simultaneously (in the same cycle). I...