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Published 20 hours ago • verified publisher icon openhwgroup

Generate separate per-target logs when simulating.

Open zchamski opened this issue 1 year ago • 1 comments

  • verif/sim/Makefile (veri-testharness): Don't add target name to waveform file name.
    (vcs-uvm): Ditto.
  • verif/sim/cva6.py (run_assembly): Add target name to log file name.
    (run_elf): Ditto.
    (run_c): Ditto.
    (iss_sim): Ditto.
    (iss_cmp): Ditto.

zchamski avatar Feb 23 '24 17:02 zchamski

:x: failed run, report available here.

github-actions[bot] avatar Feb 23 '24 17:02 github-actions[bot]

:x: failed run, report available here.

github-actions[bot] avatar Mar 01 '24 16:03 github-actions[bot]

:x: failed run, report available here.

github-actions[bot] avatar Mar 05 '24 15:03 github-actions[bot]

:heavy_check_mark: successful run, report available here.

github-actions[bot] avatar Mar 05 '24 17:03 github-actions[bot]