Partial assignment of `Logic` indices

[mkorbel1]

Motivation

In SystemVerilog and some other HDLs/generator frameworks (e.g. Chisel) there are APIs for assigning an element/range of a bus/array where the index is itself a signal. This implies significant muxing hardware, but has a nice API. ROHD should have a similar API.

Desired solution

Perhaps some sort of expansion on withSet APIs to accept Logic in addition to just int.

Alternatives considered

No response

Additional details

No response