Add SystemVerilog generation control for top of module definition

[mkorbel1]

Motivation

There are some cases where the top of the module definition may need to be modified slightly, but not entirely. For example, adding package imports (in case they are necessary for some other custom systemverilog macro, for example) at the top of the module. It would be nice to expose some configurability, probably through SystemVerilog to control that type of thing.

Desired solution

Add a hook so that things can be added at the "top" of a Module in generated SV, or a way to control/override the top of the definition (module name, parameters, ports, etc.).

Alternatives considered

No response

Additional details

No response