SystemVerilog block labels

[lucasphillips]

Description & Motivation

For ROHD classes which use begin/end to define blocks in generated SystemVerilog, support tagging the block with an optional label.

This is helpful to generate SystemVerilog which passes certain strict linting checks, and for compatibility with compilers which require labeled blocks.

Related Issue(s)

#146

Testing

Added a new set of tests which generate different types of blocks with labels and compile/compare the generated SystemVerilog.

Backwards-compatibility

No. The new parameters are optional.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes. Requires description of new parameters and explanation of the feature.