rohd
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Swizzle/Subset for LogicNet's
Motivation
There's currently no way to swizzle or grab a subset of a LogicNet
(or similarly array net) and have the result also be a net that is capable of bidirectional signaling.
Desired solution
Make it so that swizzles and subsets of nets behave as nets, ideally with identical APIs
Alternatives considered
No response
Additional details
The verilog generation needs to be different too