Consts that `inferWidth` to 0-width generate SystemVerilog with 0-width

[mkorbel1]

Describe the bug

For example, when shifting by an integer (e.g. << 0), it can generate code in SV like << 0'h0, which is not valid SystemVerilog.

To Reproduce

No response

Expected behavior

A couple of things:

• When shifting by 0, just don't do anything. This probably folds into part of https://github.com/intel/rohd/issues/429
• When generating SV of a 0-width constant, make it 1-bit instead.

Actual behavior

0'h0 illegal SV

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

Related issues: https://github.com/intel/rohd/issues/57 https://github.com/intel/rohd-cosim/issues/9 https://github.com/intel/rohd/issues/429 https://github.com/intel/rohd/issues/111