verilog-ethernet icon indicating copy to clipboard operation
verilog-ethernet copied to clipboard
verified publisher icon alexforencich

RTL Linting with Verilator -Wall

Open chili-chips-ba opened this issue 9 months ago • 1 comments

https://github.com/chili-chips-ba/wireguard-fpga/issues/14#issue-2879563883

chili-chips-ba avatar Feb 26 '25 03:02 chili-chips-ba

FYI this library is being deprecated, to be superseded by https://github.com/fpganinja/taxi . Note that the license is different (CERN OHL strongly reciprocal with an option for a commercial license, instead of MIT/BSD). Since it's written in System Verilog and I'm using Verilator as the simulator, many of these lint issues have already been fixed.

alexforencich avatar Feb 26 '25 03:02 alexforencich