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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
While creating an environment in vunit with System Verilog testbench, my simulation fails with error showing "Internal error: Cannot find 'enabled_test_cases' key". I checked everything and looks fine for me....
Merging coverage reports is [supported by nvc](https://www.nickg.me.uk/nvc/manual.html#Coverage_processing_options) but trying it in my run.py gives me `RuntimeError: This simulator does not support merging coverage`. I was able to do it manually...
``` ========================================================================================= FAILURES ========================================================================================== _______________________________________ TestLicense.test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct _______________________________________ self = def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct( self, ): for file_name in find_licensed_files(): code = ostools.read_file(file_name) > self._check_license(code, file_name) tests/lint/test_license.py:51: _ _ _ _ _ _...
This fixes #944 by trying to execute an original version (case-insensitive for VHDL compatibility) with the fall-back for use with Verilog and non-lower-case module names.
Hello, when I run VUnit test the ModelSim spits out a warning regarding the `string_ops` The warning is: `\vunit\vhdl\string_ops\src\string_ops.vhd(565): (vopt-1083) Implicit array operator "=" always returns FALSE (left length 1...
This minimal VUnit testbench succeeds with Modelsim, but fails with GHDL. However, when I try to reproduce the error with standalone GHDL (without VUnit), it seems to work fine. Here...
when generating code-coverage reports, the call to `results.merge_coverage()` fails when the supplied parameter `file_name` is a path, where the basepath doesn't exist yet. In order to not clutter the source-path,...
I am working with a codebase that splits out entity files and architecture files to support multiple architectures. So, for many files there is file.vhd for entity declaration, and file-rtl.vhd,...
I have found that vunit don't build full dependency between verilog and vhdl #929. I have updated project.py to also check if a instance is a VHDL-instance. I have also...
Updating questasim from 2020.1_1 to 2022.4_2 breakes the test 'tb_uart_lib.tb_uart_rx.test_receives_one_byte': ``` # 73810000 ps - check - ERROR - Got 1110_1110 (238). Expected 0111_0111 (119). ``` And I expect many...
