Cannot find 'enabled_test_cases'

[dsp20]

While creating an environment in vunit with System Verilog testbench, my simulation fails with error showing "Internal error: Cannot find 'enabled_test_cases' key". I checked everything and looks fine for me. Can you guess where could be the problem? I have created vunit simulation environment with System Verilog testbench previously and never faced such problem there

[LarsAsplund]

Can you provide a minimal working example for this?

[piotrva]

I had the same issue. Updating my simulator (ActiveHDL in my case - was working on vesrion 11, updated to version 14) solved this issue. After the update I deleted vunit_out folder and restarted the PC.

We resolved this isse with students of AGH UST Kraków ;)