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VUnit is a unit testing framework for VHDL/SystemVerilog

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Hi we have big designs with a lot of this warnings WARNING - /sim_lib/xxxxxxx.vhd: failed to find a primary design unit 'all' in library 'yyyyyyy' the syntax is use library_name.package_name.all;...

Enhancement
Parsing

I am trying to run Incisive 15.20 with Vunit but I get syntax errors when compiling the vunit_lib library as shown below: ![vunit_incisive_error_mmsig1](https://user-images.githubusercontent.com/50879593/58595047-09c08400-8235-11e9-9f10-fe0e800f38e1.JPG) ![vunit_incisive_error_mmsig2](https://user-images.githubusercontent.com/50879593/58595050-0b8a4780-8235-11e9-8c20-83189de9b298.JPG) The MMSIG error is described as:...

Simulator support

The VHDL Vivado example fails to generate the Vivado project with Vivado 2022.1: ``` PS C:\git\vunit\examples\vhdl\vivado> python generate_vivado_project.py vivado -nojournal -nolog -notrace -mode batch -source C:\git\vunit\examples\vhdl\vivado\tcl\generate_project.tcl -tclargs C:\git\vunit\examples\vhdl\vivado myproject Traceback...

Within the file vsim_simulator_mixin.py The **file_path** can help to source some other files from the same directory like: do $file_path/wave.do ..... @staticmethod` def _source_tcl_file(file_name, config, message): """ Create TCL to...

I have a testbench that requires some stimuli files. With other simulators (Modelsim, Questa) I have made a simple configuration that copies these files in the `simulator_output_path` and they work...

The simulation completes after 1ms. Logging with trace messages shows that _test_runner_cleanup_ passes the entry gate after 1ms without a lock being released. It works as expected if the delay...

This PR contains work toward enabling embedded Python code within VHDL For the first iteration I've focused on providing the lowest possible threshold for embedded Python and I found that...

Closes #963 Added block design parsing and generation based on https://gitlab.com/tsfpga/tsfpga/-/issues/74. 1) Requires creating `tcl` file through `write_bd_tcl` for open block designs 2) Resulting `tcl` should be located together with...

Hello, I have declared an attribute to mark my testbench. Also, in my run.py script I have a piece of code that generates vivado output products before code is compiled....

Hello @LarsAsplund. I worked on a new Sphinx extension, which can render junit XML files as tables in a Sphinx based documentation. This would allow you to: * display Python...