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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
Hi everybody, I've been using VUnit for a few years now. It is a really good tool especially due to the simulator independence. However, it would be really good if...
Hi guys, thank you for the open source project. We are using the project in several of our projects and we are really satisfied with it. We are also heavily...
I'm using attributes to set, which tests to perform. Typically I have bunch of tests tagged by user attribute .disabled, and my automatic python script is running all the tests...
As discussed in gitter (sorry I don't know how to link the conversation), I want to know which testbenches depend on some desired VHDL/Verilog files. This code does exactly that,...
* This creates a single source of truth for finding modelsim.ini. It is now possible to use MODELSIM=/path/to/custom/modelsim.ini and both ModelSim and vunit will use that. (The VUNIT_MODELSIM_INI environment variable...
We are developing an alternative wave form viewer: https://gitlab.com/surfer-project/surfer and once it is mature enough, it would be nice to add support for it in VUnit. Right now there are...
What if I want to a Python Script controlling the Simulation. For example, what if I want to compare results of two .txt files produced by TB in python and...
I am trying to run my simulation on the `ghdl:vunit/llvm-master` docker image but I am getting this error. ``` Traceback (most recent call last): File "/opt/venv/lib/python3.11/site-packages/vunit/test/runner.py", line 244, in _run_test_suite...
I recently was getting black boxes because in my instantiation of a component, I had port map lines like ``` mask => mask(j)(G_DWIDTH/8-1 downto 0), ``` This was because the...
