Fix issues when trying to parameterize Verilog modules

[piotrva]

This fixes #944 by trying to execute an original version (case-insensitive for VHDL compatibility) with the fall-back for use with Verilog and non-lower-case module names.

[piotrva]

Hi, any chance for having someone look at this PR? We use VUnit in our company and for now we had to switch to my unofficial branch.

[oscargus]

I think it maybe is better to either:

1. Move the case-handling to get_test_bench
2. Do try-except on get_test_bench only and then only check KeyError.

[piotrva]

@oscargus I modified it as you suggested.

[oscargus]

Thanks! (I should probably have mentioned that I cannot approve or merge anything, but I think/hope that the suggested changes increases the chance of having it merged...)

[piotrva]

Can you possibly contact someone who is in charge of such approvals? This issue is preventing us for use of official VUnit repo in our workflow what is suboptimal at least...

[oscargus]

I can try to ping in @LarsAsplund and @kraigher . My impression is that they have been quite busy recently though. (There may be other people that have the correct powers as well.)

[piotrva]

Any chance to have this fix merged any time soon?