fix dependency for vhdl instances inside (Sysytem) verilog modules

[roynil]

I have found that vunit don't build full dependency between verilog and vhdl #929.

I have updated project.py to also check if a instance is a VHDL-instance. I have also updated verilog/parser.py to parse interfaces as modules (which they basically are).

tox -e py38-unit,py38-acceptance-modelsim

passes (questa 2023.4) with the exception of tb_uart_lib.tb_uart_rx.test_receives_one_byte (due to #889)