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VUnit
VUnit is a unit testing framework for VHDL/SystemVerilog
Linked with issue #818 The proposed modifications on the `codec` package are retro-compatible. The `tb_codec.vhd` has not been modified to underline this. The tb of the `com` package `tb_com_codec.vhd` has...
__Objective:__ Lifting of the `codec` packages: + Adding comments + Harmonizing names when applicable + Documentation + Add support for 64bits `integer` (VHDL 2019) (the codec must adapt itself depending...
I'm getting an error with ActiveHDL 11.1: ``` === Command output: === COMP96 WARNING COMP96_0048: "This function may complete without return statement." "C:/Users/Glen.Nicholls/AppData/Local/Programs/Python/Python37/Lib/site-packages/vunit/vhdl/osvvm/ScoreboardPkg_slv_c.vhd" 1795 5 COMP96 WARNING COMP96_0048: "This function...
The documentation in https://vunit.github.io/verification_components/user_guide.html mostly shows what's available, but not really how to use theses verification components. I have also found this example: https://github.com/VUnit/vunit/tree/master/examples/vhdl/axi_dma/src/test but it is only minimally documented.
I've been using protected types to create a few VCIs (currently, I2C for a 'ram' component and I2S). It was meant to be used as this, but could surely be...
It seems that the AXI lite write slave does not support unaligned transfers (If an address in unaligned it is clipped down to the lower boundary), the slave memory also...
Hello, It seems that there's a problem with the way AXI4 Lite master detects bus idle condition. To trigger this bug it's enough to have this code in your testbench:...
Add set_simulator method exposed to user for simpler switching between simulators #793
The vivado.py python script pulls the path to the vivado binary from either the user's path or from method argument, rather than from a env variable like the simulator paths....
Just like queue the `dict_t` should support values of any standard and IEEE type in a type safe manner.
